TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-3
The conditional instructions provide efficient alternatives to conditional jumps around very short sequences of
code. All of the conditional instructions use a condition operand that controls the execution of the instruction.
The condition operand is a data register, with any non-zero value interpreted as TRUE, and a zero value
interpreted as FALSE. For the CADD and CSUB instructions, the addition/subtraction is performed if the condition
is TRUE. For the CADDN and CSUBN instructions it is performed if the condition is FALSE.
The SEL instruction copies one of its two source operands to its destination operand, with the selection of source
operands determined by the value of the condition operand (This operation is the same as the C language ?
operation). A typical use might be to record the index value yielding the larger of two array elements:
index_max = (a[i] > a[j]) ? i : j;
If one of the two source operands in a SEL instruction is the same as the destination operand, then the SEL
instruction implements a simple conditional move. This occurs often in source statements of the general form:
if (<condition>) then <variable> = <expression>;
Provided that <expression> is simple, it is more efficient to evaluate it unconditionally into a source register, using
a SEL instruction to perform the conditional assignment, rather than conditionally jumping around the assignment
statement.
2.1.8 Logical
The TriCore architecture provides a complete set of two-operand, bit-wise logic operations. In addition to the AND,
OR, and XOR functions, there are the negations of the output; NAND, NOR, and XNOR, and negations of one of
the inputs; ANDN and ORN (the negation of an input for XOR is the same as XNOR).
2.1.9 Count Leading Zeros, Ones and Signs
To provide efficient support for normalization of numerical results, prioritization, and certain graphics operations,
three Count Leading instructions are provided:
• CLZ (Count Leading Zeros)
• CLO (Count Leading Ones)
• CLS (Count Leading Signs)
These instructions are used to determine the amount of left shifting necessary to remove redundant zeros, ones,
or signs.
Note:The CLS instruction returns the number of leading redundant signs, which is the number of leading signs
minus one.
The following special cases are defined:
• CLZ(0) = 32, CLO(-1) = 32
• CLS(0) = CLS(-1) = 31
For example, CLZ returns the number of consecutive zeros starting from the most significant bit of the value in the
source data register. In the example shown in Figure 2-1, there are seven zeros in the most significant portion of
the input register. If the most significant bit of the input is a 1, CLZ returns 0:
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