Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-418
UPDFL
Update Flags
Description
The UPDFL instruction takes two 8-bit data fields from D[a], and uses them to update the PSW user flag bits (PSW
[31:24]) that the FPU uses to store its exception flags and rounding mode in. D[a][15:8] are the update mask field;
a ‘1’ in a given bit position indicates that the corresponding PSW user flag bit is to be updated. D[a][7:0] are the
update value field. These bits supply the values to be written to the PSW user flags bits, in the positions specified
by the mask field.
Example: Changing the current PSW[25:24] (Rounding mode) to round toward +?, without modifying any of the
current exception flag settings, can be accomplished by loading the literal value 0301
H
into register D[0], and
issuing the instruction, UPDFL D[0].
UPDFLD[a] (RR)
set_FS = (PSW.FS & ~D[a][15]) | (D[a][7] & D[a][15]);
set_FI = (PSW.FI & ~D[a][14]) | (D[a][6] & D[a][14]);
set_FV = (PSW.FV & ~D[a][13]) | (D[a][5] & D[a][13]);
set_FZ = (PSW.FZ & ~D[a][12]) | (D[a][4] & D[a][12]);
set_FU = (PSW.FU & ~D[a][11]) | (D[a][3] & D[a][11]);
set_FX = (PSW.FX & ~D[a][10]) | (D[a][2] & D[a][10]);
set_RM = (PSW.RM & ~D[a][9:8]) | (D[a][1:0] & D[a][9:8]);
PSW.[31:24] = {set_FS, set_FI, set_FV, set_FZ, set_FU, set_FX, set_RM};
Exception Flags
Examples
updfl d1
See Also
-
FS PSW.FS = set_FS;
FI PSW.FI = set_FI;
FV PSW.FV = set_FV;
FZ PSW.FZ = set_FZ;
FU PSW.FU = set_FU;
FX PSW.FX = set_FX;
31
a
28 27
0C
H
20 19
-
18 17
1
H
16 15
-
12 11
a
8 7
4B
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English