TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-400
ADD.F
Add Float
Description
Add the contents of data register D[a] to the contents of data register D[d]. Put the result in data register D[c]. The
operands and result are single precision IEEE-754-1985 floating-point numbers. If either operand is a NaN (quiet
or signalling), then the return result will be the quiet NaN 7FC00000
H
.
ADD.FD[c], D[d], D[a] (RRR)
arg_a = denorm_to_zero(f_real(D[a]);
arg_b = denorm_to_zero(f_real(D[d]);
if(is_nan(D[a]) OR is_nan(D[d])) then result = QUIET_NAN;
else if(is_pos_inf(D[a]) AND is_neg_inf(D[d])) then result = ADD_NAN;
else if(is_neg_inf(D[a]) AND is_pos_inf(D[d])) then result = ADD_NAN;
else {
precise_result = add(arg_a,arg_b);
normal_result = denorm_to_zero(precise_result);
rounded_result = ieee754_round(normal_result, PSW.RM);
result = ieee754_32bit_format(rounded_result);
}
D[c] = result[31:0];
Exception Flags
Examples
add.f d3, d1, d2
See Also
SUB.F
FS if(set_FI OR set_FV OR set_FU OR set_FX) then PSW.FS = 1 else PSW.FS = 0;
FI if(is_s_nan(D[a]) OR is_s_nan(D[d])) then set_FI = 1 else set_FI = 0;
if(set_FI) then PSW.FI = 1;
FV if(rounded_result >= 2
128
) then set_FV = 1 else set_FV = 0;
if(set_FV) then PSW.FV = 1;
FZ Not set by this instruction.
FU if(fp_abs(precise_result) < 2
-126
) then set_FU = 1 else set_FU = 0;
if(set_FU) then PSW.FU = 1;
FX if(precise_result != f_real(result)) then set_FX = 1 else set_FX = 0;
if(set_FX AND !set_FI) then PSW.FX = 1;
31
c
28 27
d
24 23
02
H
20 19
-
18 17
1
H
16 15
-
12 11
a
8 7
6B
H
0
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