Infineon TriCore TC1.6P - LD.Q - Load Half-Word Signed Fraction

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-165
LD.Q
Load Half-word Signed Fraction
Description
Load the half-word contents of the memory location specified by the addressing mode into the most-significant
half-word of data register D[a], setting the 16 least-significant bits of D[a] to zero.
LD.QD[a], off18 (ABS)(Absolute Addressing Mode)
EA = {off18[17:14],14b'0,off18[13:0]};
D[a] = {M(EA, halfword), 16’h0000};
LD.QD[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
D[a] = {M(EA, halfword), 16’h0000};
LD.QD[a], P[b] (BO)(Bit-reverse Addressing Mode)
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
D[a] = {M(EA, halfword), 16’h0000};
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
LD.QD[a], P[b], off10 (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA0 = A[b] + index;
D[a] = {M(EA, halfword), 16’h0000};
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index + length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
LD.QD[a], A[b], off10 (BO)(Post-increment Addressing Mode)
31
off18[9:6]
28 27
00
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
a
8 7
45
H
0
31
off10[9:6]
28 27
28
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
-
28 27
08
H
22 21
-
16 15
b
12 11
a
8 7
29
H
0
31
off10[9:6]
28 27
18
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
29
H
0