Infineon TriCore TC1.6P - EQANY.B - Equal any Byte; EQANY.H - Equal any Half-Word

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-100
EQANY.B
Equal Any Byte
EQANY.H
Equal Any Half-word
Description
Compare each byte (EQANY.B) or half-word (EQANY.H) of D[a] with the corresponding byte or half-word of either
D[b] (instruction format RR) or const9 (instruction format RC). If the logical OR of the Boolean results from each
comparison is TRUE, set the least-significant bit of D[c] to 1 and clear the remaining bits to zero; otherwise clear
all bits in D[c]. Const9 is sign-extended.
EQANY.BD[c], D[a], const9 (RC)
result_byte3 = (D[a][31:24] == sign_ext(const9)[31:24]);
result_byte2 = (D[a][23:16] == sign_ext(const9)[23:16]);
result_byte1 = (D[a][15:8] == sign_ext(const9)[15:8]);
result_byte0 = (D[a][7:0] == sign_ext(const9)[7:0]);
result = result_byte3 OR result_byte2 OR result_byte1 OR result_byte0;
D[c] = zero_ext(result);
EQANY.BD[c], D[a], D[b] (RR)
result_byte3 = (D[a][31:24] == D[b][31:24]);
result_byte2 = (D[a][23:16] == D[b][23:16]);
result_byte1 = (D[a][15:8] == D[b][15:8]);
result_byte0 = (D[a][7:0] == D[b][7:0]);
result = result_byte3 OR result_byte2 OR result_byte1 OR result_byte0;
D[c] = zero_ext(result);
EQANY.HD[c], D[a], const9 (RC)
result_halfword1 = (D[a][31:16] == sign_ext(const9)[31:16]);
result_halfword0 = (D[a][15:0] == sign_ext(const9)[15:0]);
result = result_halfword1 OR result_halfword1;
D[c] = zero_ext(result);
EQANY.HD[c], D[a], D[b] (RR)
31
c
28 27
56
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
56
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
31
c
28 27
76
H
21 20
const9
12 11
a
8 7
8B
H
0