TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
V1.0 2013-07
User Manual (Volume 2) 1-1
1 Instruction Set Information
This chapter contains descriptions of all TriCoreâ„¢ instructions. The instruction mnemonics are grouped into
families of similar or related instructions, then listed in alphabetical order within those groups.
Notes
1. All instructions and operators are signed unless stated ‘unsigned’.
2. Information specific to 16-bit instructions is shown in a box with a grey background.
1.1 Instruction Syntax
The syntax definition specifies the operation to be performed and the operands used. Instruction operands are
separated by commas.
1.1.1 Operand Definitions
The Operand definitions are detailed in the following table.
1.1.2 Instruction Mnemonic
An instruction mnemonic is composed of up to three basic parts.
• A base operation
– Specifies the instructions basic operation. For example: ADD for addition, J for jump and LD for memory
load. Some instructions such as OR.EQ, have more than one base operation, separated by a period (.).
• An operation modifier
– Specifies the operation more precisely. For example: ADDI for addition using an immediate value, or JL for
a jump that includes a link. More than one operation modifier may be used for some instructions (ADDIH for
example).
• An operand (data type) modifier.
– Gives the data type of the source operands. For example: ADD.B for byte addition, JZ.A for a jump using an
address register and LD.H for a half-word load. The data type modifier is separated by a period (.).
Using the ADDS.U instruction as an example:
• ‘ADD’ is the base operation.
• ‘S’ is an operation modifier specifying that the result is saturated.
• ‘U’ is a data type modifier specifying that the operands are unsigned.
Table 1-1 Operand Definitions
Operand Definition
D[n] Data register n
A[n] Address register n
E[n] Extended data register n containing a 64-bit value made from an even/odd pair of registers
(D[n], D[n+1]). The format is little endian.
E[n][63:32] = D[n+1][31:0]; E[n][31:0] = D[n][31:0]
dispn Displacement value of ‘n’ bits, used to form the effective address in branch instructions
constn Constant value of ‘n’ bits, used as instruction operand
offn Offset value of ‘n’ bits, used to form the effective address in Load and Store instructions
pos1, pos2 Used to specify the position in a bit field instruction
pos Pos (position) is used with width to define a field
width Specifies the width of the bit field in bit field instructions
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