Infineon TriCore TC1.6P - MIN - Minimum Value; MIN.U - Minimum Value Unsigned

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-223
MIN
Minimum Value
MIN.U
Minimum Value Unsigned
Description
If the contents of data register D[a] are less than the contents of either data register D[b] (instruction format RR)
or const9 (instruction format RC), then put the contents of D[a] in data register D[c]; otherwise put the contents of
either D[b] (format RR) or const9 (format RC) in to D[c]. The operands are treated as either signed (MIN) or
unsigned (MIN.U) 32-bit integers.
MIND[c], D[a], const9 (RC)
D[c] = (D[a] < sign_ext(const9)) ? D[a] : sign_ext(const9);
MIND[c], D[a], D[b] (RR)
D[c] = (D[a] < D[b]) ? D[a] : D[b];
MIN.UD[c], D[a], const9 (RC)
D[c] = (D[a] < zero_ext(const9)) ? D[a] : zero_ext(const9); // unsigned
MIN.UD[c], D[a], D[b] (RR)
D[c] = (D[a] < D[b]) ? D[a] : D[b]; // unsigned
Status Flags
Examples
min d3, d1, d2
min d3, d1, #126
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
SAV Not set by these instructions.
31
c
28 27
18
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
18
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
31
c
28 27
19
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
19
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0