TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-9
2.4.2 Special Case: -1 * -1
When multiplying two maximum-negative 1.15 format values (-1), the result is the positive number (+1). For
example:
8000H * 8000H = 4000 0000H
This is correctly interpreted in Q format as:
-1(1.15 format) * -1(1.15 format) = +1 (2.30 format)
However, when the result is shifted left by 1 (left-justified), the result is 8000 0000H. This is incorrectly interpreted
as:
-1(1.15 format) * -1(1.15 format) = -1 (1.31 format)
To avoid this problem, the result of a Q format operation (-1 * -1) that has been left-shifted by 1, is saturated to the
maximum positive value. Therefore:
8000H * 8000H = 7FFF FFFFH
This is correctly interpreted in Q format as:
-1(1.15 format) * -1(1.15 format) = (nearest representation of)+1 (1.31 format)
This operation is completely transparent to the user and does not set the overflow flags. It applies only to 16-bit
by 16-bit multiplies and does not apply to 16 by 32-bit or 32 by 32-bit multiplies.
2.4.3 Guard Bits
When accumulating sums (in filter calculations for example), guard bits are often required to prevent overflow.
The instruction set directly supports the use of one guard bit when using a 32-bit accumulator (2.30 format, where
left shift by 1-bit of result is not requested).
When more guard bits are required a register pair (64-bits) can be used. In that instance the intermediate result
(also in 2.30 format, where left shift by 1-bit is not performed) is left shifted by 16-bits giving effectively a 18.46
format.
2.4.4 Rounding
Rounding is used to retain the 16 most-significant bits of a 32-bit result.
Rounding is implemented by adding 1 to bit 15 of a 32-bit intermediate result.
If the operation writes a full 32-bit register (i.e. is not a component of a packed half-word operation), it then clears
the lower 16-bits.
2.4.5 Overflow and Saturation
Saturation on overflow is available on all DSP instructions.
2.4.6 Sticky Advance Overflow and Block Scaling if FFT
The Sticky Advance Overflow (SAV) bit, which is set whenever an overflow ‘almost’ occurred, can be used in block
scaling of intermediate results during an FFT calculation.
Before each pass of applying a butterfly operation, the SAV bit is cleared.
After the pass the SAV bit is tested. If it is set then all of the data is scaled (using an arithmetic right shift) before
starting the next pass.
This procedure gives the greatest dynamic range for intermediate results without the risk of overflow.
2.4.7 Multiply and MAC
The available instructions for multiplication include:
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