TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-46
BSPLIT
Bit Split
Description
Split data register D[a] into a data register pair E[c] such that all the even bits of D[a] are in the even register and
all the odd bits of D[a] are in the odd register.
BSPLITE[c], D[a] (RR)
E[c][63:48] = 0000
H
;
E[c][47:40] = {D[a][31], D[a][29], D[a][27], D[a][25], D[a][23], D[a][21], D[a][19], D[a][17]};
E[c][39:32] = {D[a][15], D[a][13], D[a][11], D[a][9], D[a][7], D[a][5], D[a][3], D[a][1]};
E[c][31:16] = 0000
H
;
E[c][15:8] = {D[a][30], D[a][28], D[a][26], D[a][24], D[a][22], D[a][20], D[a][18], D[a][16]};
E[c][7:0] = {D[a][14], D[a][12], D[a][10], D[a][8], D[a][6], D[a][4], D[a][2], D[a][0]};
Status Flags
Examples
bsplit e2, d5
See Also
BMERGE
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
09
H
20 19
-
18 17
0
H
16 15
-
12 11
a
8 7
4B
H
0
To Next Page
Loading...
Need help?
General
