TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-83
DISABLE
Disable Interrupts
Description
Note: DISABLE can only be executed in User-1 mode or Supervisor mode.
Disable interrupts by clearing Interrupt Enable bit (ICR.IE) in the Interrupt Control Register. Optionaly update D[a]
with the ICR.IE value prior to clearing.
DISABLE(SYS)
ICR.IE = 0; // disables all interrupts
DISABLED[a] (SYS)
D[a][31:1] = 0H;
D[a][0] = ICR.IE;
ICR.IE = 0; // disables all interrupts
Status Flags
Examples
disable
See Also
ENABLE, BISR, RESTORE
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
-
28 27
0D
H
22 21
-
12 11
-
8 7
0D
H
0
31
-
28 27
0F
H
22 21
-
12 11
a
8 7
0D
H
0
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