TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-271
MTCR
Move To Core Register
Description
Note:This instruction can only be executed in Supervisor mode.
Move the value in data register D[a] to the Core Special Function Register (CSFR) selected by the value const16.
The CSFR address is a const16 byte offset from the CSFR base address. It must be word-aligned (the least-
significant two bits are zero). Non-aligned address have an undefined effect.
The MTCR instruction can not be used to access GPRs. Attempting to update a GPR with this instruction will have
no effect.
An MTCR instruction should be followed by an ISYNC instruction. This ensures that all instructions following the
MTCR see the effects of the CSFR update.
MTCRconst16, D[a] (RLC)
CR[const16] = D[a];
Status Flags
Examples
mtcr 4, d1
See Also
MFCR, RSTV
C if (const16 == FE04
H
) then PSW.C = D[a][31];
V if (const16 == FE04
H
) then PSW.V = D[a][30];
SV if (const16 == FE04
H
) then PSW.SV = D[a][29];
AV if (const16 == FE04
H
) then PSW.AV = D[a][28];
SAV if (const16 == FE04
H
) then PSW.SAV = D[a][27];
31
-
28 27
const16
12 11
a
8 7
CD
H
0
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