Infineon TriCore TC1.6P - SWAP.W - Swap with Data Register

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-379
SWAP.W
Swap with Data Register
Description
Swap atomically the contents of data register D[a] and the memory word specified by the addressing mode.
SWAP.Woff18, D[a] (ABS)(Absolute Addressing Mode)
EA = {off18[17:14], 14b'0, off18[13:0]};
tmp = M(EA, word);
M(EA, word) = D[a];
D[a] = tmp[31:0];
SWAP.WA[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
tmp = M(EA, word);
M(EA, word) = D[a];
D[a] = tmp[31:0];
SWAP.WP[b], D[a] (BO)(Bit-reverse Addressing Mode)
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
tmp = M(EA, word);
M(EA, word) = D[a];
D[a] = tmp[31:0];
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
SWAP.WP[b], off10, D[a] (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
31
off18[9:6]
28 27
00
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
a
8 7
E5
H
0
31
off10[9:6]
28 27
20
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
49
H
0
31
-
28 27
00
H
22 21
-
16 15
b
12 11
a
8 7
69
H
0
31
off10[9:6]
28 27
10
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
69
H
0