TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-405
FTOQ31
Float to Fraction
Description
Subtracts D[b] from the exponent of the floating-point input value D[a] and converts the result to the Q31fraction
format. The result is stored in D[c]. The rounding mode used for the conversion is defined by the PSW.RM field.
The exponent adjustment is a 9-bit two’s complement number taken from D[b][8:0], with a value of [-256, 255].
D[b][31:9] is ignored.
Q31 fraction format is a 32-bit two’s complement format which represents a value in the range [-1,1).
• Bit 31 represents -1
• Bit 30 represents +1/2
• Bit 29 represents +1/4
• Bit 28 represents +1/8
•etc.
FTOQ31D[c], D[a], D[b] (RR)
arg_a = denorm_to_zero(f_real(D[a]);
if(is_nan(D[a])) then result = 0;
else precise_result = mul(arg_a, 2
-D[b][8:0]
);
if(precise_result > q_real(7FFFFFFF
H
)) then result = 7FFFFFFF
H
;
else if(precise_result < -1.0) then result = 80000000
H
;
else result = round_to_q31(precise_result);
D[c] = result[31:0];
Exception Flags
Examples
ftoq31 d3, d1, d2
See Also
Q31TOF, FTOQ31Z
FS if(set_FI OR set_FX) then PSW.FS = 1 else PSW.FS = 0;
FI if((precise_result > q_real(7FFFFFFF
H
)) OR (precise_result < -1.0) OR is_nan(D[a])) then set_FI = 1 else
set_FI = 0;
if(set_FI) then PSW.FI = 1;
FV Not set by this instruction.
FZ Not set by this instruction.
FU Not set by this instruction.
FX if(f_real(D[a]) != q_real(result)) then set_FX = 1 else set_FX = 0;
if(set_FX AND !set_FI) then PSW.FX = 1;
31
c
28 27
11
H
20 19
-
18 17
1
H
16 15
b
12 11
a
8 7
4B
H
0
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