TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-170
LDLCX
Load Lower Context
Description
Load the contents of the memory block specified by the addressing mode into registers A[2]-A[7] and D[0]-D[7].
This operation is normally used to restore GPR values that were saved previously by an STLCX instruction.
Note:The effective address specified by the addressing mode must be aligned on a 16-word boundary. For this
instruction the addressing mode is restricted to absolute (ABS) or base plus short offset (BO).
Note:This instruction may not be used to access peripheral space.
LDLCXoff18 (ABS)(Absolute Addressing Mode)
EA = {off18[17:14],14b'0,off18[13:0]};
{dummy, dummy, A[2:3], D[0:3], A[4:7], D[4:7]} = M(EA, 16-word);
LDLCXA[b], off10 (BO) (Base + Short Index Addressing Mode)
EA = A[b] + sign_ext(off10);
{dummy, dummy, A[2:3], D[0:3], A[4:7], D[4:7]} = M(EA, 16-word);
Status Flags
Examples
-
See Also
LDUCX, RSLCX, STLCX, STUCX, SVLCX, BISR
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
off18[9:6]
28 27
02
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
-
8 7
15
H
0
31
off10[9:6]
28 27
24
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
49
H
0
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