Infineon TriCore TC1.6P - MUL.Q - Multiply Q Format

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-277
MUL.Q
Multiply Q Format
Description
Multiply two signed 16-bit or 32-bit values and put the product (left justified if n == 1) into a 32-bit or 64-bit register.
There are two cases of 16*16 operations, four cases of 16*32 operations and two cases of 32*32 operations.
Note that n should only take the values 0 or 1, any other value returns an undefined result. If (n == 1) then 8000
H
* 8000
H
= 7FFFFFFF
H
(for signed 16-bit * 16-bit multiplications only).
MUL.QD[c], D[a], D[b], n (RR1)
(32 * 32)Up --> 32
result = ((D[a] * D[b]) << n) >> 32;
D[c] = result[31:0]; // Fraction
MUL.QE[c], D[a], D[b], n (RR1)
(32 * 32) --> 64
result = (D[a] * D[b]) << n;
E[c] = result[63:0]; // Multi-precision fraction
MUL.QD[c], D[a], D[b] L, n (RR1)
(32 * 16L)Up --> 32
result = ((D[a] * D[b][15:0]) << n) >> 16;
D[c] = result[31:0]; // Fraction
MUL.QE[c], D[a], D[b] L, n (RR1)
(32 * 16L) --> 64
result = (D[a] * D[b][15:0]) << n;
E[c] = result[63:0]; // Multi-precision accumulator
MUL.QD[c], D[a], D[b] U, n (RR1)
(32 * 16U)Up --> 32
31
c
28 27
02
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
1B
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
01
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
19
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0