Infineon TriCore TC1.6P - Page 323

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-276
E[c] = {result_word1[31:0], result_word0[31:0]}; // Packed fraction
MUL.HE[c], D[a], D[b] UU, n (RR1)
(16L * 16U || 16U * 16U) --> 32||32
sc1 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
result_word1 = sc1 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
result_word0 = sc0 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
E[c] = {result_word1[31:0], result_word0[31:0]}; // Packed fraction
Status Flags
Examples
-
See Also
-
C Not set by this instruction.
V The PSW.V status bit is cleared.
SV Not set by this instruction.
AV aov_word1 = result_word1[31] ^ result_word1[30];
aov_word0 = result_word0[31] ^ result_word0[30];
advanced_overflow = aov_word1 OR aov_word0;
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
31
c
28 27
1B
H
18 17
n
16 15
b
12 11
a
8 7
B3
H
0