Infineon TriCore TC1.6P - SHA - Arithmetic Shift

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-340
SHA
Arithmetic Shift
Description
If shift count specified through contents of either D[b] (instruction format RR) or const9 (instruction format RC) is
greater than or equal to zero, then left-shift the value in D[a] by the amount specified by shift count. The vacated
bits are filled with zeros and bits shifted out are discarded. If the shift count is less than zero, right-shift the value
in D[a] by the absolute value of the shift count. The vacated bits are filled with the sign-bit (the most significant bit)
and bits shifted out are discarded. Put the result in D[c].
The shift count is a 6-bit signed number, derived from either D[b][5:0] or const9[5:0]. The range for shift count is
therefore -32 to +31, allowing a shift left up to 31 bit positions and a shift right up to 32 bit positions (a shift right
by 32 bits leaves all zeros or all ones in the result, depending on the sign bit). On all 1-bit or greater shifts (left or
right), PSW.C is set to the logical-OR of the shifted out bits. On zero-bit shifts C is cleared.
SHAD[c], D[a], const9 (RC)
if (const9[5:0] >= 0) then {
carry_out = const9[5:0] ? (D[a][31:32 - const9[5:0]] != 0) : 0;
result = D[a] << const9[5:0];
} else {
shift_count = 0 - const9[5:0];
msk = D[a][31] ? (((1 << shift_count) - 1) << (32 - shift_count)) : 0;
result = msk | (D[a] >> shift_count);
carry_out = (D[a][shift_count - 1:0] != 0);
}
D[c] = result[31:0];
SHAD[c], D[a], D[b] (RR)
if (D[b][5:0] >= 0) then {
carry_out = D[b][5:0] ? (D[a][31:32 - D[b][5:0]] != 0) : 0;
result = D[a] << D[b][5:0];
} else {
If shift count specified through the value const4 is greater than or equal to zero, then left-shift the value in D[a]
by the amount specified by the shift count. The vacated bits are filled with zeros and bits shifted out are discarded.
If the shift count is less than zero, right-shift the value in D[a] by the absolute value of the shift count. The vacated
bits are filled with the sign-bit (the most significant bit) and bits shifted out are discarded. Put the result in D[a].
The shift count is a 6-bit signed number, derived from the sign-extension of const4[3:0]. The resulting range for
the shift count is therefore -8 to +7, allowing a shift left up to 7 bit positions, and a shift right up to 8 bit positions.
On all shifts of 1-bit or greater (left or right), PSW.C is set to the logical-OR of the shifted out bits. On zero-bit
shifts C is cleared.
31
c
28 27
01
H
21 20
const9
12 11
a
8 7
8F
H
0
31
c
28 27
01
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0F
H
0