Infineon TriCore TC1.6P - Page 386

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-339
SH.OR.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][30:0], (D[a][pos1] OR D[b][pos2])};
SH.ORN.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][30:0], (D[a][pos1] OR !(D[b][pos2]))};
SH.XNOR.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][30:0], !(D[a][pos1] XOR D[b][pos2])};
SH.XOR.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][30:0], (D[a][pos1] XOR D[b][pos2])};
Status Flags
Examples
sh.and.t d3, d1, 4, d2, 7
sh.andn.t d3, d1, 4, d2, 7
sh.nand.t d3, d1, 4, d2, 7
sh.nor.t d3, d1, 4, d2, 7
sh.or.t d3, d1, 4, d2, 7
sh.orn.t d3, d1, 4, d2, 7
sh.xnor.t d3, d1, 4, d2, 7
sh.xor.t d3, d1, 4, d2, 7
See Also
AND.AND.T, AND.ANDN.T, AND.NOR.T, AND.OR.T, OR.AND.T, OR.ANDN.T, OR.NOR.T, OR.OR.T
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
SAV Not set by these instructions.
31
c
28 27
pos2
23 22
01
H
21 20
pos1
16 15
b
12 11
a
8 7
27
H
0
31
c
28 27
pos2
23 22
01
H
21 20
pos1
16 15
b
12 11
a
8 7
A7
H
0
31
c
28 27
pos2
23 22
02
H
21 20
pos1
16 15
b
12 11
a
8 7
A7
H
0
31
c
28 27
pos2
23 22
03
H
21 20
pos1
16 15
b
12 11
a
8 7
A7
H
0