TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-32
AND.AND.T
Accumulating Bit Logical AND-AND
AND.ANDN.T
Accumulating Bit Logical AND-AND-Not
AND.NOR.T
Accumulating Bit Logical AND-NOR
AND.OR.T
Accumulating Bit Logical AND-OR
Description
Compute the logical AND, ANDN, NOR or OR of the value in bit pos1 of data register D[a] and bit pos2 of D[b].
Then compute the logical AND of that result and bit 0 of D[c], and put the result in bit 0 of D[c]. All other bits in D[c]
are unchanged.
AND.AND.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][31:1], D[c][0] AND (D[a][pos1] AND D[b][pos2])};
AND.ANDN.TD[c], D[a,] pos1, D[b], pos2 (BIT)
D[c] = {D[c][31:1], D[c][0] AND (D[a][pos1] AND !D[b][pos2])};
AND.NOR.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][31:1], D[c][0] AND !(D[a][pos1] OR D[b][pos2])};
AND.OR.TD[c], D[a], pos1, D[b], pos2 (BIT)
D[c] = {D[c][31:1], D[c][0] AND (D[a][pos1] OR D[b][pos2])};
Status Flags
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
31
c
28 27
pos2
23 22
00
H
21 20
pos1
16 15
b
12 11
a
8 7
47
H
0
31
c
28 27
pos2
23 22
03
H
21 20
pos1
16 15
b
12 11
a
8 7
47
H
0
31
c
28 27
pos2
23 22
02
H
21 20
pos1
16 15
b
12 11
a
8 7
47
H
0
31
c
28 27
pos2
23 22
01
H
21 20
pos1
16 15
b
12 11
a
8 7
47
H
0