TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-4
Figure 2-1 Operation of the CLZ Instruction
2.1.10 Shift
The shift instructions support multi-bit shifts.
The shift amount is specified by a signed integer (n), which may be the contents of a register or a sign-extended
constant in the instruction.
If n >= 0, the data is shifted left by n[4:0]; otherwise, the data is shifted right by (-n)[4:0].
The (logical) shift instruction SH, shifts in zeros for both right and left shifts.
The arithmetic shift instruction SHA, shifts in sign bits for right shifts and zeros for left shifts.
The arithmetic shift with saturation instruction SHAS, will saturate (on a left shift) if the sign bits that are shifted out
are not identical to the sign bit of the result.
2.1.11 Bit-Field Extract and Insert
The TriCore architecture supports three, bit-field extract instructions:
• EXTR (Extract bit field)
• EXTR.U (Extract bit field unsigned)
• DEXTR (Extract from Double Register)
The INSERT instruction is described on Page 2-6.
EXTR and EXTR.U
The EXTR and EXTR.U instructions extract width consecutive bits from the source, beginning with the bit number
specified by the pos (position) operand. The width and pos can be specified by two immediate values, by an
immediate value and a data register, or by a data register pair.
The EXTR instruction fills the most-significant bits of the result by sign-extending the bit field extracted (duplicating
the most-significant bit of the bit field). See Figure 2-2.
EXTR.U zero-fills the most significant (32-w) bits of the result. See Figure 2-3.
110
TC1044
000000111000001101 101010111010110
Data Register
Count Leading Zero Logic
1 1100
To Next Page
Loading...
Need help?
General
