Infineon TriCore TC1.6P - LDMST - Load-Modify-Store

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-171
LDMST
Load-Modify-Store
Description
The atomic Load-Modify-Store implements a store under a mask of a value to the memory word, whose address
is specified by the addressing mode. Only those bits of the value E[a][31:0] where the corresponding bits in the
mask E[a][63:32] are set, are stored into memory. The value and mask may be generated using the IMASK
instruction.
LDMSToff18, E[a] (ABS)(Absolute Addressing Mode)
EA = {off18[17:14], 14b'0,off18[13:0]};
M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]);
LDMSTA[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]);
LDMSTP[b], E[a] (BO)(Bit-reverse Addressing Mode)
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]);
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
LDMSTP[b], off10, E[a] (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]);
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index + length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
31
off18[9:6]
28 27
01
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
a
8 7
E5
H
0
31
off10[9:6]
28 27
21
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
49
H
0
31
-
28 27
01
H
22 21
-
16 15
b
12 11
a
8 7
69
H
0
31
off10[9:6]
28 27
11
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
69
H
0