Infineon TriCore TC1.6P - DVADJ - Divide-Adjust

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-85
DVADJ
Divide-Adjust
Description
Divide-adjust the contents of the formatted data register E[d] using the divisor in D[b] and store the result in E[c].
E[d][63:32] contains the sign-extended final remainder from a previous DVSTEP instruction and E[d][31:0]
contains the sign-extended final quotient in ones complement format. The DVADJ instruction converts the final
quotient to twos complement format by adding one if the final quotient is negative, and corrects for a corner case
that occurs when dividing a negative dividend that is an integer multiple of the divisor. The corner case is resolved
by setting the remainder E[d][63:32] to zero and increasing the magnitude of the quotient E[d][31:0] by one. Note
that the increment for converting a negative ones complement quotient to twos complement, and the decrement
of a negative quotient in the corner case (described above), cancel out.
Note:This operation must not be performed at the end of an unsigned divide sequence.
DVADJE[c], E[d], D[b] (RRR)
q_sign = E[d][63] ^ D[b][31];
x_sign = E[d][63];
eq_pos = x_sign & (E[d][63:32] == D[b]);
eq_neg = x_sign & (E[d][63:32] == -D[b]);
if((q_sign & ~eq_neg) | eq_pos) {
quotient = E[d][31:0] + 1;
} else {
quotient = E[d][31:0];
}
if(eq_pos | eq_neg) {
remainder = 0;
} else {
remainder = E[d][63:32];
}
gt = abs(E[d][63:32]) > abs(D[b]);
eq = !E[d][63] AND (abs(E[d][63:32] == abs(D[b]));
overflow = eq | gt;
if(overflow) {
E[c] = 64'bx;
} else {
E[c] = {remainder[31:0],quotient[31:0]};
}
31
c
28 27
d
24 23
0D
H
20 19
-
18 17
0
H
16 15
b
12 11
-
8 7
6B
H
0