Infineon TriCore TC1.6P - NAND - Bitwise NAND

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-288
NAND
Bitwise NAND
Description
Compute the bitwise NAND of the contents of data register D[a] and either data register D[b] (instruction format
RR) or const9 (instruction format RC). Put the result in data register D[c]. The const9 value is zero-extended.
NANDD[c], D[a], const9 (RC)
D[c] = ~(D[a] & zero_ext(const9));
NANDD[c], D[a], D[b] (RR)
D[c] = ~(D[a] & D[b]);
Status Flags
Examples
nand d3, d1, d2
nand d3, d1, #126
See Also
AND, ANDN, NOR, NOT (16-bit), OR, ORN, XNOR, XOR
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
09
H
21 20
const9
12 11
a
8 7
8F
H
0
31
c
28 27
09
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0F
H
0