Infineon TriCore TC1.6P - MADDM.H - Packed Multiply-Add Q Format Multi-Precision; MADDMS.H - Packed Multiply-Add Q Format Multi-Precision, Saturated

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-198
MADDM.H
Packed Multiply-Add Q Format Multi-precision
MADDMS.H
Packed Multiply-Add Q Format Multi-precision, Saturated
Description
Perform two multiplications of two signed 16-bit (half-word) values. Add the two products (left justified if n == 1)
left-shifted by 16, to a signed 64-bit value and put the result in a 64-bit register. The MADDMS.H result is saturated
on overflow. There are four cases of half-word multiplication.
Note that n should only take the values 0 or 1, any other value returns an undefined result. If (n == 1) then 8000
H
* 8000
H
= 7FFFFFFF
H
(for signed 16-bit * 16-bit multiplications only).
MADDM.HE[c], E[d], D[a], D[b] LL, n (RRR1)
64 + (16U * 16L) + (16L * 16L) --> 64
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
result_word1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
result_word0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result = E[d] + ((result_word1 + result_word0) << 16);
E[c] = result[63:0]; // Multi-precision accumulator
MADDM.HE[c], E[d], D[a], D[b] LU, n (RRR1)
64 + (16U * 16L) + (16L * 16U) --> 64
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
result_word1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
result_word0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
result = E[d] + ((result_word1 + result_word0) << 16);
E[c] = result[63:0]; // Multi-precision accumulator
MADDM.HE[c], E[d], D[a], D[b] UL, n (RRR1)
64 + (16U * 16U) + (16L * 16L) --> 64
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
result_word1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
31
c
28 27
d
24 23
1E
H
18 17
n
16 15
b
12 11
a
8 7
83
H
0
31
c
28 27
d
24 23
1D
H
18 17
n
16 15
b
12 11
a
8 7
83
H
0
31
c
28 27
d
24 23
1C
H
18 17
n
16 15
b
12 11
a
8 7
83
H
0