Infineon TriCore TC1.6P - ST.B - Store Byte

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-349
ST.B
Store Byte
Description
Store the byte value in the eight least-significant bits of data register D[a] to the byte memory location specified by
the addressing mode.
ST.Boff18, D[a] (ABS)(Absolute Addressing Mode)
EA = {off18[17:14], 14b'0, off18[13:0]};
M(EA, byte) = D[a][7:0];
ST.BA[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
M(EA, byte) = D[a][7:0];
ST.B P[b], D[a] (BO)(Bit-reverse Addressing Mode)
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
M(EA, byte) = D[a][7:0];
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
ST.BP[b], off10, D[a] (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA0 = A[b] + index;
M(EA, byte) = D[a][7:0];
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index + length : new_index % length;
Store the byte value in the eight least-significant bits of either data register D[a] (instruction format SSR, SSR0
or BO) or D[15] (instruction format SRO) to the byte memory location specified by the addressing mode.
31
off18[9:6]
28 27
00
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
a
8 7
25
H
0
31
off10[9:6]
28 27
20
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
89
H
0
31
-
28 27
00
H
22 21
-
16 15
b
12 11
a
8 7
A9
H
0
31
off10[9:6]
28 27
10
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
A9
H
0