TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-22
The LDUCX instruction (Load Upper Context) loads registers A[10] to A[15] and D[8] to D[15]. The PSW and link
word fields in the saved context in memory are ignored. The PSW, FCX, and PCXI are unaffected.
The STLCX instruction (Store Lower Context) stores the same context information that is saved with an explicit
lower context save operation: Registers A[2] to A[7] and D[0] to D[7], together with the Return Address (RA) in
A[11] and the PCXI. The LDLCX instruction (Load Lower Context) loads registers A[2] through A[7] and D[0]
through D[7]. The saved return address and the link word fields in the context stored in memory are ignored.
Registers A[11] (Return Address), FCX, and PCXI are not affected.
The Context Load and Store instructions may not be used to access peripheral space. A MEM trap will be triggered
if such an access is attempted.
2.12 System Instructions
The system instructions allow User mode and Supervisor mode programs to access and control various system
services, including interrupts and the TriCore’s debugging facilities. There are also instructions that read and write
the core registers, for both User and Supervisor-only mode programs. There are special instructions for the
memory management system.
2.12.1 System Call
The SYSCALL instruction generates a system call trap, providing a secure mechanism for User mode application
code to request Supervisor mode services.
The system call trap, like other traps, vectors to the trap handler table, using the three-bit hardware-furnished trap
class ID as an index.
The trap class ID for system call traps is six.
The Trap Identification Number (TIN) is specified by an immediate constant in the SYSCALL instruction and serves
to identify the specific Supervisor mode service that is being requested.
2.12.2 Synchronization Primitives (DYSNC and ISYNC)
The TriCore architecture provides two synchronization primitives, DYSNC and ISYNC. These primitives provide a
mechanism to software through which it can guarantee the ordering of various events within the machine.
DSYNC
The DSYNC primitive provides a mechanism through which a data memory barrier can be implemented.
The DSYNC instruction guarantees that all data accesses associated with instructions semantically prior to the
DSYNC instruction are completed before any data memory accesses associated with an instruction semantically
after DSYNC are initiated. This includes all accesses to the system bus and local data memory.
ISYNC
The ISYNC primitive provides a mechanism through which the following can be guaranteed:
• If an instruction semantically prior to ISYNC makes a software visible change to a piece of architectural state,
then the effects of this change are seen by all instructions semantically after ISYNC.
– For example, if an instruction changes a code range in the protection table, the use of an ISYNC guarantees
that all instructions after the ISYNC are fetched and matched against the new protection table entry.
• All cached states in the pipeline, such as loop cache buffers, are invalidated.
The operation of the ISYNC instruction is as follows:
1. Wait until all instructions semantically prior to the ISYNC have completed.
2. Flush the CPU pipeline and cancel all instructions semantically after the ISYNC.
3. Invalidate all cached state in the pipeline.
4. Re-Fetch the next instruction after the ISYNC.
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