TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-329
SH
Shift
Description
Shift the value in D[a] by the amount specified by shift count. If the shift count specified through the contents of
either D[b] (instruction format RR) or const9 (instruction format RC) is greater than or equal to zero, then left-shift.
Otherwise right-shift by the absolute value of the shift count. Put the result in D[c]. In both cases the vacated bits
are filled with zeros and the bits shifted out are discarded.
The shift count is a 6-bit signed number, derived from either D[b][5:0] or const9[5:0]. The range for the shift count
is therefore -32 to +31, allowing a shift left up to 31 bit positions and to shift right up to 32 bit positions (Note that
a shift right by 32 bits leaves zeros in the result).
SHD[c], D[a], const9 (RC)
D[c] = (const9[5:0] >= 0) ? D[a] << const9[5:0] : D[a] >> (-const9[5:0]);
SHD[c], D[a], D[b] (RR)
D[c] = (D[b][5:0] >= 0) ? D[a] << D[b][5:0] : D[a] >> (-D[b][5:0]);
SHD[a], const4 (SRC)
Status Flags
If the shift count specified through the value const4 is greater than or equal to zero, then left-shift the value in
D[a] by the amount specified by the shift count. Otherwise right-shift the value in D[a] by the absolute value of
the shift count. Put the result in D[a].
In both cases, the vacated bits are filled with zeros and bits shifted out are discarded.
The shift count is a 4-bit signed number, derived from the sign-extension of const4[3:0]. The resulting range for
the shift count therefore is -8 to +7, allowing a shift left up to 7-bit positions and to shift right up to 8-bit positions.
shift_count = sign_ext(const4[3:0]);
D[a] = (shift_count >= 0) ? D[a] << shift_count : D[a] >> (-shift_count);
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
00
H
21 20
const9
12 11
a
8 7
8F
H
0
31
c
28 27
00
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0F
H
0