Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-287
MULR.Q
Multiply Q Format with Rounding
Description
Multiply two signed 16-bit (half-word) values and put the rounded result (left justified if n == 1) into a 32-bit register.
The lower half-word is cleared.
Note that n should only take the values 0 or 1, any other value returns an undefined result. If (n == 1) then 8000
H
* 8000
H
= 7FFFFFFF
H
(for signed 16-bit * 16-bit multiplications only).
MULR.QD[c], D[a] L, D[b] L, n (RR1)
(16L * 16L) rounded --> 32
sc = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
result = sc ? 7FFFFFFF
H
: (((D[a][15:0] * D[b][15:0]) << n) + 8000
H
);
D[c] = {result[31:16], 16’b0}; // Short fraction
MULR.QD[c], D[a] U, D[b] U, n (RR1)
(16U * 16U) rounded --> 32
sc = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
result = sc ? 7FFFFFFF
H
: (((D[a][31:16] * D[b][31:16]) << n) + 8000
H
);
D[c] = {result[31:16], 16’b0}; // Short fraction
Status Flags
Examples
-
See Also
-
C Not set by this instruction.
V The PSW.V status bit is cleared.
SV Not set by this instruction.
AV advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
07
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
06
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English