Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-75
CMOVN (16-bit)
Conditional Move-Not (16-bit)
Description
CMOVND[a], D[15], const4 (SRC)
CMOVND[a], D[15], D[b] (SRR)
Status Flags
Examples
See Also
CADD, CADDN, CMOV (16-bit), CSUB, CSUBN, SEL, SELN
If the contents of data register D[15] are zero, copy the contents of either data register D[b] (instruction format
SRR) or const4 (instruction format SRC) to data register D[a]; otherwise the contents of D[a] is unchanged. The
const4 value is sign-extended to 32-bits.
D[a] = ((D[15] == 0) ? sign_ext(const4) : D[a]);
D[a] = ((D[15] == 0) ? D[b] : D[a]);
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
cmovn d1, dl5, d2
cmovn d1, dl5, #6
15
const4
12 11
a
8 7
EA
H
0
15
b
12 11
a
8 7
6A
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English