TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-327
SEL
Select
Description
If the contents of data register D[d] are non-zero, copy the contents of data register D[a] to data register D[c];
otherwise copy the contents of either D[b] (instruction format RRR) or const9 (instruction format RCR), to D[c].
The value const9 (instruction format RCR) is sign-extended.
SELD[c], D[d], D[a], const9 (RCR)
D[c] = ((D[d] != 0) ? D[a] : sign_ext(const9));
SELD[c], D[d], D[a], D[b] (RRR)
D[c] = ((D[d] != 0) ? D[a] : D[b]);
Status Flags
Examples
sel d3, d4, d1, d2
sel d3, d4, d1, #126
See Also
CADD, CADDN, CMOV (16-bit), CMOVN (16-bit), CSUB, CSUBN, SELN
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
d
24 23
04
H
21 20
const9
12 11
a
8 7
AB
H
0
31
c
28 27
d
24 23
04
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
2B
H
0
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