Infineon TriCore TC1.6P - ADDS - Add Signed with Saturation

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-22
ADDS
Add Signed with Saturation
Description
Add the contents of data register D[a] to the value in either data register D[b] (instruction format RR) or const9
(instruction format RC) and put the result in data register D[c]. The operands are treated as signed, 32-bit integers,
with saturation on signed overflow. The value const9 is sign-extended before the addition is performed.
ADDSD[c], D[a], const9 (RC)
result = D[a] + sign_ext(const9);
D[c] = ssov(result, 32);
ADDSD[c], D[a], D[b] (RR)
result = D[a] + D[b];
D[c] = ssov(result, 32);
ADDSD[a], D[b], (SRR)
Status Flags
Examples
adds d3, d1, d2
adds d3, d1, #126
Add the contents of data register D[b] to the contents of data register D[a] and put the result in data register D[a].
The operands are treated as signed 32-bit integers, with saturation on signed overflow.
result = D[a] + D[b];
D[a] = ssov(result, 32);
C Not set by this instruction.
V overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
02
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
02
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
15
b
12 11
a
8 7
22
H
0