TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-2
2.1.3 Multiply and Multiply-Add
For the multiplication of 32-bit integers, the available mnemonics are:
• MUL (Multiply Signed)
• MULS (Multiply Signed with Saturation)
• MULS.U (Multiply Unsigned with Saturation)
These translate to machine instructions producing either 32-bit or 64-bit results, depending on whether the
destination operand encoded in the assembly instruction is a single data register D[n] (where n = 0, 1, …15), or
an extended data register E[n] (where n = 0, 2, …14).
In those cases where the number of bits in the destination is 32-bit, the result is taken from the lower bits of the
product. This corresponds to the standard ‘C’ multiplication of two integers.
The MAC instructions (Multiplication with Accumulation) follow the instruction forms for multiplication; MADD,
MADDS, MADD.U, MADDS.U, and MSUB, MSUBS, MSUB.U, MSUBS.U.
In all cases a third source operand register is specified, which provides the accumulator to which the multiplier
results are added.
2.1.4 Division
Division of 32-bit by 32-bit integers is supported for both signed and unsigned integers. Because an atomic divide
instruction would require an excessive number of cycles to execute, a divide-step sequence is used, which keeps
interrupt latency down. The divide step sequence allows the divide time to be proportional to the number of
significant quotient bits expected.
The sequence begins with a Divide-Initialize instruction: DVINIT(.U), DVINIT.H(U) or DVINIT.B(U), depending on
the size of the quotient and on whether the operands are to be treated as signed or unsigned. The divide
initialization instruction extends the 32-bit dividend to 64-bits, then shifts it left by 0, 16 or 24-bits. It simultaneously
shifts in that many copies of the quotient sign bit to the low-order bit positions. 4, 2 or 1 Divide-Step instructions
(DVSTEP or DVSTEP.U) then follow. Each Divide-Step instruction develops eight bits of quotient.
At the end of the divide step sequence, the 32-bit quotient occupies the low-order word of the 64-bit dividend
register pair, and the remainder is held in the high-order word. If the divide operation was signed, the Divide-Adjust
instruction (DVADJ) is required to perform a final adjustment of negative values. If the dividend and the divisor are
both known to be positive, the DVADJ instruction can be omitted.
2.1.5 Absolute Value, Absolute Difference
A common operation on data is the computation of the absolute value of a signed number or the absolute value
of the difference between two signed numbers. These operations are provided directly by the ABS and ABSDIF
instructions. There is a version of each instruction which saturates when the result is too large to be represented
as a signed number.
2.1.6 Min, Max, Saturate
Instructions are provided that directly calculate the minimum or maximum of two operands. The MIN and MAX
instructions are used for signed integers, and MIN.U and MAX.U are used for unsigned integers.
The SAT instructions can be used to saturate the result of a 32-bit calculation before storing it in a byte or half-
word, in memory or a register.
2.1.7 Conditional Arithmetic Instructions
Conditional arithmetic instructions are:
• CADD (Conditional Add) and CADDN (Conditional Add-Not)
• CSUB (Conditional Subtract) and CSUBN (Conditional Subtract-Not)
• SEL (Select) and SELN (Select-Not)
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