Infineon TriCore TC1.6P - RSTV - Reset Overflow Bits

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
RSTV
Reset Overflow Bits
Description
Reset overflow status flags in the Program Status Word (PSW).
RSTV(SYS)
V1.0 2013-07
User Manual (Volume 2) 3-320
PSW.{V, SV, AV, SAV} = {0, 0, 0, 0};
Status Flags
Examples
rstv
See Also
BISR, DISABLE, ENABLE, MTCR, TRAPV, TRAPSV
C Not set by this instruction.
V The PSW.V status bit is cleared.
SV The PSW.SV status bit is cleared.
AV The PSW.AV status bit is cleared.
SAV The PSW.SAV status bit is cleared.
31
-
28 27
00
H
22 21
-
12 11
-
8 7
2F
H
0