TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
V1.0 2013-07
User Manual (Volume 2) 1-2
Some instructions, typically 16-bit instructions, use a General Purpose Register (GPR) as an implicit source or
destination.
Note:In the syntax section of the instruction descriptions, the implicit registers are included as explicit operands.
However they are not explicitly encoded in the instructions.
1.1.3 Operation Modifiers
The operation modifiers are shown in the following table. The order of the modifiers in this table is the same as the
order in which they appear as modifiers in an instruction mnemonic.
Table 1-2 Implicit Operand Definitions
Operand Definition
D[15] Implicit Data register for many 16-bit instructions
A[10] Stack Pointer (SP)
A[11] Return Address (RA) register for CALL, JL, JLA and JLI instructions, and Return PC value
on interrupts
A[15] Implicit Address Register for many 16-bit Load/Store instructions
Table 1-3 Operation Modifiers
Operation
Modifier
Name Description Example
C Carry Use and update PSW carry bit ADDC
I Immediate Large immediate ADDI
H High Word Immediate value put in most-significant bits ADDIH
S Saturation Saturate result ADDS
X Carry out Update PSW carry bit ADDX
EQ Equal Comparison equal JEQ
GE Greater than Comparison greater than or equal JGE
L Link Record link (jump subroutine) JL
A Absolute Absolute (jump) JLA
I Indirect Register indirect (jump) JLI
LT Less than Comparison less than JLT
NE Not equal Comparison not equal JNE
D Decrement Decrement counter JNED
I Increment Increment counter JNEI
Z Zero Use zero immediate JNZ
M Multi-precision Multi-precision result (>32-bit) in Q format MULM
R Round Round result MULR
N Not Logical NOT SELN
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