TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-117
ISYNC
Synchronize Instructions
Description
The ISYNC instruction forces completion of all previous instructions, then flushes the CPU pipelines and
invalidates any cached pipeline state before proceeding to the next instruction.
Note:I-cache is not invalidated by ISYNC.
Note:An ISYNC instruction should follow a MTCR instruction. This ensures that all instructions following the
MTCR see the effects of the CSFR update.
ISYNC(SYS)
-
Status Flags
Examples
isync
See Also
DSYNC
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
-
28 27
13
H
22 21
-
12 11
-
8 7
0D
H
0
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