Infineon TriCore TC1.6P - Page 163

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-116
INSERTD[c], D[a], D[b], E[d] (RRRR)
width = E[d][36:32];
mask = (2
width
-1) << E[d][4:0];
D[c] = (D[a] & ~mask) | ((D[b] << E[d][4:0]) & mask);
If E[d][4:0] + E[d][36:32] > 32, then the result is undefined.
INSERTD[c], D[a], D[b], D[d], width (RRRW)
mask = (2
width
-1) << D[d][4:0];
D[c] = (D[a] & ~mask) | ((D[b] << D[d][4:0]) & mask);
If D[d][4:0] + width > 32, then the result is undefined.
Status Flags
Examples
insert d3, d1, d2, e4
insert d3, d1, d2, d4, #8
insert d3, d1, d2, #16,#8
insert d3, d1, 0, e4
insert d3, d1, 0, d4, #8
insert d3, d1, 0, #16, #8
See Also
DEXTR, EXTR, EXTR.U, INS.T, INSN.T
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
d
24 23
00
H
21 20
-
16 15
b
12 11
a
8 7
17
H
0
31
c
28 27
d
24 23
00
H
21 20
width
16 15
b
12 11
a
8 7
57
H
0