TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-102
EQZ.A
Equal Zero Address
Description
If the contents of address register A[a] are equal to zero, set the least significant bit of D[c] to one and clear the
remaining bits to zero; otherwise clear all bits in D[c].
EQZ.AD[c], A[a] (RR)
D[c] = (A[a] == 0);
Status Flags
Examples
eqz.a d3, a4
See Also
EQ.A, GE.A, LT.A, NE, NEZ.A
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
48
H
20 19
-
18 17
-
16 15
-
12 11
a
8 7
01
H
0