TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-29
ADDX
Add Extended
Description
Add the contents of data register D[a] to the contents of either data register D[b] (instruction format RR) or const9
(instruction format RC) and put the result in data register D[c]. The operands are treated as 32-bit signed integers.
The const9 value is sign-extended before the addition is performed. The PSW carry bit is set to the value of the
ALU carry out.
ADDXD[c], D[a], const9 (RC)
result = D[a] + sign_ext(const9);
D[c] = result[31:0];
carry_out = carry(D[a],sign_ext(const9),0);
ADDXD[c], D[a], D[b] (RR)
result = D[a] + D[b];
D[c] = result[31:0];
carry_out = carry(D[a],D[b],0);
Status Flags
Examples
addx d3, d1, d2
addx d3, d1, #126
See Also
ADD, ADDC, ADDI, ADDIH, ADDS, ADDS.U
C PSW.C = carry_out;
V overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
04
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
04
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
To Next Page
Loading...
Need help?
General
