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TriCore

TC1.6P & TC1.6E

32-bit Unified Processor Core

Instruction Set

V1.0 2013-07

User Manual (Volume 2) 3-334

SH.H

Shift Packed Half-words

Description

If the shift count specified through the contents of either D[b] (instruction format RR) or const9 (instruction format

RC) is greater than or equal to zero, then left-shift each half-word in D[a] by the amount specified by shift count.

Otherwise, right-shift each half-word in D[a] by the absolute value of the shift count. Put the result in D[c]. In both

cases the vacated bits are filled with zeros and bits shifted out are discarded. For these shifts, each half-word is

treated individually, and bits shifted out of a half-word are not shifted in to the next half-word.

The shift count is a signed number, derived from the sign-extension of either D[b][4:0] (instruction format RR) or

const9[4:0] (instruction format RC). The range for the shift count is therefore -16 to +15. The result for a shift count

of -16 for half-words is zero.

SH.HD[c], D[a], const9 (RC)

shift_count = sign_ext(const9[4:0]);

result_halfword1 = (shift_count >= 0) ? D[a][31:16] << shift_count : D[a][31:16] >> (0 - shift_count);

result_halfword0 = (shift_count >= 0) ? D[a][15:0] << shift_count : D[a][15:0] >> (0 - shift_count);

D[c] = {result_halfword1[15:0], result_halfword0[15:0]};

SH.HD[c], D[a], D[b] (RR)

shift_count = sign_ext(D[b][4:0]);

result_halfword1 = (shift_count >= 0) ? D[a][31:16] << shift_count : D[a][31:16] >> (0 - shift_count);

result_halfword0 = (shift_count >= 0) ? D[a][15:0] << shift_count : D[a][15:0] >> (0 - shift_count);

D[c] = {result_halfword1[15:0], result_halfword0[15:0]};

Status Flags

Examples

sh.h d3, d1, d2

sh.h d3, d1, #12

Infineon TriCore TC1.6P User Manual

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