Infineon TriCore TC1.6P - ANDN - Bitwise AND-Not

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-41
ANDN
Bitwise AND-Not
Description
Compute the bitwise AND of the contents of data register D[a] and the ones complement of the contents of either
data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The
const9 value is zero-extended to 32-bits.
ANDND[c], D[a], const9 (RC)
D[c] = D[a] & ~zero_ext(const9);
ANDND[c], D[a], D[b] (RR)
D[c] = D[a] & ~D[b];
Status Flags
Examples
andn d3, d1, d2
andn d3, d1, #126
See Also
AND, NAND, NOR, NOT (16-bit), OR, ORN, XNOR, XOR
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
0E
H
21 20
const9
12 11
a
8 7
8F
H
0
31
c
28 27
0E
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0F
H
0