Infineon TriCore TC1.6P - TRAPSV - Trap on Sticky Overflow

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-384
TRAPSV
Trap on Sticky Overflow
Description
If the PSW sticky overflow status flag (PSW.SV) is set, generate a trap to the vector entry for the sticky overflow
trap handler (SOV-trap).
TRAPSV(SYS)
if PSW.SV == 1 then trap(SOVF);
Status Flags
Examples
trapsv
See Also
RSTV, SYSCALL, TRAPV
C Not set by this instruction.
V Not set by this instruction.
SV PSW.SV is read, but not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
-
28 27
15
H
22 21
-
12 11
-
8 7
0D
H
0