TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-365
STLCX
Store Lower Context
Description
Store the contents of registers A[2] to A[7], D[0] to D]7], A[11] (return address) and PCXI, to the memory block
specified by the addressing mode. For this instruction, the addressing mode is limited to absolute (ABS) or base
plus short offset (BO).
Note:The effective address (EA) specified by the addressing mode must be aligned on a 16-word boundary.
Note:This instruction may not be used to access peripheral space.
STLCXoff18 (ABS)(Absolute Addressing Mode)
EA = {off18[17:14], 14b'0, off18[13:0]};
M(EA,16-word) = {PCXI, A[11], A[2:3], D[0:3], A[4:7], D[4:7]};
STLCXA[b], off10 (BO)(Base + Short Index Addressing Mode)
EA = A[b] + sign_ext(off10)[9:0]};
M(EA,16-word) = {PCXI, A[11], A[2:3], D[0:3], A[4:7], D[4:7]};
Status Flags
Examples
-
See Also
LDLCX, LDUCX, RSLCX, STUCX, SVLCX, BISR
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
off18[9:6]
28 27
00
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
-
8 7
15
H
0
31
off10[9:6]
28 27
26
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
49
H
0
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