Infineon TriCore TC1.6P - Page 411

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-364
ST.WA[b], D[a] (SSR)(Post-increment Addressing Mode)
ST.WA[15], off4, D[a] (SSRO)
Status Flags
Examples
st.w [a0+]2, d0
st.w [a0+]22, d0
See Also
ST.A, ST.B, ST.D, ST.DA, ST.H, ST.Q
M(A[b], word) = D[a];
A[b] = A[b] + 4;
M(A[15] + zero_ext(4 * off4), word) = D[a];
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
15
b
12 11
a
8 7
64
H
0
15
off4
12 11
a
8 7
68
H
0