TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-331
SH.EQ
Shift Equal
Description
Left shift D[c] by one. If the contents of data register D[a] are equal to the contents of either data register D[b]
(instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one; otherwise set
the least-significant bit of D[c] to 0.
The value const9 (format RC) is sign-extended.
SH.EQD[c], D[a], const9 (RC)
D[c] = {D[c][30:0], (D[a] == sign_ext(const9))};
SH.EQD[c], D[a], D[b] (RR)
D[c] = {D[c][30:0], (D[a] == D[b])};
Status Flags
Examples
sh.eq d3, d1, d2
sh.eq d3, d1, #126
See Also
SH.GE, SH.GE.U, SH.LT, SH.LT.U, SH.NE
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
37
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
37
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
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