TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-24
Programs executing in Supervisor mode can use the 16-bit BISR instruction (Begin Interrupt Service Routine) to
save the lower context of the current task, set the current CPU priority number and re-enable interrupts (which are
disabled by the processor when an interrupt is taken).
2.12.5 Return (RET) and Return From Exception (RFE) Instructions
The RET (Return) instruction is used to return from a function that was invoked via a CALL instruction. The RFE
(Return From Exception) instruction is used to return from an interrupt or trap handler.
These two instructions perform very similar operations; they restore the upper context of the calling function or
interrupted task and branch to the return address contained in register A[11] (prior to the context restore
operation).
The two instructions differ in the error checking they perform for call depth management. Issuing an RFE
instruction when the current call depth (as tracked in the PSW) is non-zero, generates a context nesting error trap.
Conversely, a context call depth underflow trap is generated when an RET instruction is issued when the current
call depth is zero.
2.12.6 Trap Instructions
The Trap on Overflow (TRAPV) and Trap on Sticky Overflow (TRAPSV) instructions can be used to cause a trap
if the PSWs V and SV bits respectively, are set. See PSW (Program Status Word) Status Flags and Arithmetic
Instructions, page 2-8.
2.12.7 No-Operation (NOP)
Although there are many ways to represent a no-operation (for example, adding zero to a register), an explicit NOP
instruction is included so that it can be easily recognized.
2.13 Coprocessor (COP) Instructions
The TriCore instruction set architecture may be extended with implementation defined, application specific
instructions. These instructions are executed on dedicated coprocessor hardware attached to the coprocessor
interface.
The coprocessors operate in a similar manner to the integer instructions, receiving operands from the general
purpose data registers and able to return a result to the same registers.
The architecture supports the operation of up to four concurrent coprocessors (n = 0, 1, 2, 3). Two of these
(n = 0, 1) are reserved for use by the TriCore CPU allowing two (n = 2, 3) for use by the application hardware.
2.14 16-bit Instructions
The 16-bit instructions are a subset of the 32-bit instruction set, chosen because of their frequency of static use.
The 16-bit instructions significantly reduce static code size and therefore provide a reduction in the cost of code
memory and a higher effective instruction bandwidth. Because the 16-bit and 32-bit instructions all differ in the
primary opcode, the two instruction sizes can be freely intermixed.
The 16-bit instructions are formed by imposing one or more of the following format constraints:
• Smaller constants
• Smaller displacements
• Smaller offsets
• Implicit source, destination, or base address registers
• Combined source and destination registers (the 2-operand format)
In addition, the 16-bit load and store instructions support only a limited set of addressing modes.
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