TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-25
The registers D[15] and A[15] are used as implicit registers in many 16-bit instructions. For example, there is a
16-bit compare instruction (EQ) that puts a Boolean result in D[15], and a 16-bit conditional move instruction
(CMOV) which is controlled by the Boolean in D[15].
The 16-bit load and store instructions are limited to the register indirect (base plus zero offset), base plus offset
(with implicit base or source/destination register), and post-increment (with default offset) addressing modes. The
offset is a scaled offset. It is scaled up to 10-bit by the type of instruction (byte, half-word, word).
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