TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-8
2.3 PSW (Program Status Word) Status Flags and Arithmetic Instructions
Arithmetic instructions operate on data and addresses in registers. Status information about the result of the
arithmetic operations is recorded in the five status flags in the Program Status Word (PSW) register.
2.3.1 Usage
The status flags can be read by software using the Move From Core Register (MFCR) instruction, and can be
written using the Move to Core Register (MTCR) instruction.
Note:MTCR is only available in Supervisor mode.
The Trap on Overflow (TRAPV) and Trap on Sticky Overflow (TRAPSV) instructions can be used to cause a trap
if the respective V (overflow) and SV (sticky overflow) bits are set. The overflow bits can be cleared using the Reset
Overflow Bits instruction (RSTV).
Individual arithmetic operations can be checked for overflow by reading and testing V.
If it is only necessary to determine if an overflow occurred somewhere in an entire block of computation, then the
SV bit is reset before the block (using the RSTV instruction) and tested after completion of the block (using MFCR).
Jumping based on the overflow result is achieved by using a MFCR instruction followed by a JZ.T or JNZ.T
(conditional jump on the value of a bit) instruction.
2.3.2 Saturation
Because most signal-processing applications can handle overflow by simply saturating the result, most of the
arithmetic instructions have a saturating version for signed and unsigned overflow.
Note:Saturating versions of all instructions can be synthesized using short code sequences.
When saturation is used for 32-bit signed arithmetic overflow, if the true result of the computation is greater than
(2
31
-1) or less than -2
31
, the result is set to (2
31
-1) or -2
31
, respectively.
The bounds for 16-bit signed arithmetic are (2
15
-1) and -2
15
, and the bounds for 8-bit signed arithmetic are (2
7
-1)
and -2
7
.
When saturation is used for unsigned arithmetic, the lower bound is always zero and the upper bounds are (2
32
-1),
(2
16
-1), and (2
8
-1).
Saturation is indicated in the instruction mnemonic by an S and unsigned is indicated by a U following the period
(.). For example, the instruction mnemonic for a signed saturating addition is ADDS, and the mnemonic for an
unsigned saturating addition is ADDS.U.
2.4 DSP Arithmetic
DSP arithmetic instructions operate on 16-bit signed fractional data in the 1.15 format (also known as Q15), and
32-bit signed fractional data in 1.31 format (Q31).
Data values in this format have a single, high-order sign bit, with a value of 0 or -1, followed by an implied binary
point and fraction. Their values are in the range [-1, 1).
2.4.1 Scaling
The multiplier result can be treated in one of two ways:
• Left shifted by 1
– One sign bit is suppressed and the result is left-aligned, so conserving the input format.
•Not shifted
– The result retains its two sign bits (2.30 format). This format can be used with IIR (Infinite Impulse Response)
filters for example, in which some of the coefficients are between 1 and 2, and to have one guard bit for
accumulation.
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