TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-26
ADDS.U
Add Unsigned with Saturation
Description
Add the contents of data register D[a] to the contents of either data register D[b] (instruction format RR) or const9
(instruction format RC) and put the result in data register D[c]. The operands are treated as unsigned 32-bit
integers, with saturation on unsigned overflow. The const9 value is sign-extended.
ADDS.UD[c], D[a], const9 (RC)
result = D[a] + sign_ext(const9); // unsigned addition
D[c] = suov(result, 32);
ADDS.UD[c], D[a], D[b] (RR)
result = D[a] + D[b]; // unsigned addition
D[c] = suov(result, 32);
Status Flags
Examples
adds.u d3, d1, d2
adds.u d3, d1, #126
See Also
ADD, ADDC, ADDI, ADDIH, ADDS, ADDX
C Not set by this instruction.
V overflow = (result > FFFFFFFF
H
) OR (result < 00000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
03
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
03
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
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