Infineon TriCore TC1.6P - IMASK - Insert Mask

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-112
IMASK
Insert Mask
Description
Create a mask containing the number of bits specified by width, starting at the bit number specified by either
D[d][4:0] (instruction formats RRRW and RCRW) or pos (instruction formats RRPW and RCPW), and put the mask
in data register E[c][63:32].
Left-shift the value in either D[b] (formats RRRW and RRPW) or const4 (formats RCRW and RCPW) by the
amount specified by either D[d][4:0] (formats RRRW and RCRW) or pos (formats RRPW and RCPW) and put the
result value in data register E[c][31:0].
The value const4 is zero-extended. This mask and value can be used by the Load-Modify-Store (LDMST)
instruction to write a specified bit field to a location in memory.
IMASKE[c], const4, pos, width (RCPW)
E[c][63:32] = ((2
width
-1) << pos);
E[c][31:0] = (zero_ext(const4) << pos);
If pos + width > 32 the result is undefined.
IMASKE[c], const4, D[d], width (RCRW)
E[c][63:32] = ((2
width
-1) << D[d][4:0]);
E[c][31:0] = (zero_ext(const4) << D[d][4:0]);
If (D[d][4:0] + width) > 32 the result is undefined.
IMASKE[c], D[b], pos, width (RRPW)
E[c][63:32] = ((2
width
-1) << pos);
E[c][31:0] = (D[b][31:0] << pos);
If (pos + width) > 32 the result is undefined.
IMASKE[c], D[b], D[d], width (RRRW)
E[c][63:32] = ((2
width
-1) << D[d][4:0]);
E[c][31:0] = (D[b] << D[d][4:0]);
If (D[d][4:0] + width) > 32 the result is undefined.
31
c
28 27
pos
23 22
01
H
21 20
width
16 15
const4
12 11
-
8 7
B7
H
0
31
c
28 27
d
24 23
01
H
21 20
width
16 15
const4
12 11
-
8 7
D7
H
0
31
c
28 27
pos
23 22
01
H
21 20
width
16 15
b
12 11
-
8 7
37
H
0
31
c
28 27
d
24 23
01
H
21 20
width
16 15
b
12 11
-
8 7
57
H
0