Infineon TriCore TC1.6P - TRAPV - Trap on Overflow

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-385
TRAPV
Trap on Overflow
Description
If the PSW overflow status flag (PSW.V) is set, generate a trap to the vector entry for the overflow trap handler
(OVF trap).
TRAPV(SYS)
if PSW.V then trap(OVF);
Status Flags
Examples
trapv
See Also
RSTV, SYSCALL, TRAPSV, UNPACK
C Not set by this instruction.
V PSW.V is read, but not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
-
28 27
14
H
22 21
-
12 11
-
8 7
0D
H
0